m906-01 datasheet rev 1.3 revised 06jan2004 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 m906-01 vcso b ased g b e c lock g enerator integrated circuit systems, inc. preliminary information g eneral d escription the m906-01 is a pll (phase locked loop) based clock generator that uses an internal vcso (voltage controlled saw oscillator) to produce a very low jitter output clock. it is ideal for gigabit ethernet. the output clock (frequency of 156.25 or 187.50 mhz for example) is provided from six lvpecl clock output pairs. (specify frequency at time of order.) the accuracy of the output frequency is assured by the internal pll, which phase-locks the internal vcso to the reference input frequency ( 25 or 30 mhz for example). the input reference can either be an external crystal, utilizing the internal crystal oscillator, or a stable external clock source such as a packaged crystal oscillator. f eatures output clock frequency from 125mhz to 190mhz (consult factory for frequency availability) six identical lvpecl output pairs integrated saw (surface acoustic wave) delay line low jitter 0.7ps rms (over 12khz-20mhz) ideal for gigabit ethernet clock reference output-to-output skew < 100 ps external xtal or lvcmos reference input selectable external fe ed-through clock input stop clock control (logic 1 stops output clocks) industrial temperature grade available single 3.3v power supply small 9 x 9 mm smt (surface mount) package p in a ssignment (9 x 9 mm smt) figure 1: pin assignment s implified b lock d iagram figure 2: simplified block diagram example output frequency configurations ref clock frequency (mhz) pll ratio output frequency 1 (mhz) note 1:specify output clo ck frequency at time of order application 20 25/4 156.25 gbe 25 156.25 10gbe 30 187.50 12gbe table 1: example output frequency configurations m906-01 (top view) 1 2 3 4 5 6 7 8 9 xtal_1 / ref_in gnd stop ext_clk en_ext_clk nc nfout3 fout3 vcc nfout2 fout2 nfout1 fout1 gnd nfout0 fout0 vcc gnd xtal_2 fout4 nfout4 fout5 nfout5 vcc dnc dnc dnc nop_in op_out vc nvc nop_out op_in gnd gnd gnd 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 18 17 16 15 14 13 12 11 10 m906-01-156.25 xtal osc o 1 external crystal or reference clock input (e.g., 25 or 30mhz) lvpecl output clock pairs (e.g., 156.25 or 187.50mhz) divider external clock in p ut external clock select output clock stop control vsco frequency multiplying pll external loop filter m906-01 vcso based gbe clock generator
m906-01 datasheet rev 1.3 2 of 6 revised 06jan2004 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m906-01 vcso b ased g b e c lock g enerator preliminary information d etailed b lock d iagram figure 3: detailed block diagram p in d escriptions number name i/o configuration description 1, 2, 3, 10, 14, 26 gnd ground power supply ground connections. 4 9 op_in nop_in input external loop filter c onnections. see figure 4, external loop filter, on pg. 3. 5 8 nop_out op_out output 6 7 nvc vc input 11, 19, 33 vcc power power supply connection, connect to + 3.3 v. 12 13 fout0 nfout0 output no internal terminator clock output pairs, differential lvpecl output ( 156.25 mhz for the m906-01-156.2500 ) 15 16 fout1 nfout1 17 18 fout2 nfout2 20 21 fout3 nfout3 29 30 fout4 nfout4 31 32 fout5 nfout5 23 en_ext_clk input internal pull-down resistor 1 note 1: for typical value of in ternal pull-down resistor, see dc characteristics , pull-down on pg. 5 for typical value. logic 1 enables the ext_clk input. use logic 0 for normal operation. 24 ext_clk input external clock feed-through: 0 to 200 mhz 25 stop input internal pull-down resistor 1 logic 1 stops clock outputs. use logic 0 for normal operation. 27 xtal_1 / ref_in input internal pull-down resistor 1 external crystal connection. also accepts lvcmos/lvttl compatible clock source. 28 xtal_2 input external crystal connection. leave unconnected when driving pin 27 with external clock reference. 34, 35, 36 dnc do not connect. table 2: pin descriptions m906-01 xtal_2 xtal_1 / ref_in xtal osc ext_clk en_ext_clk stop fout2 nfout2 fout4 nfout4 fout3 nfout3 fout5 nfout5 fout0 nfout0 fout1 nfout1 r divider r = 4 phase detector vcso saw delay line phase shifter vcso c post c post vc nvc r post nop_out op_out r post r loop r loop c loop c loop r in r in op_in nop_in loop filter amplifier external loop filter components m divider m = 25 phase locked loop (pll) o 1
m906-01 datasheet rev 1.3 3 of 6 revised 06jan2004 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 m906-01 vcso b ased g b e c lock g enerator preliminary information integrated circuit systems, inc. f unctional d escription the m906-01 is a pll (phase locked loop) based clock generator that generates output clocks synchronized to an input reference clock. the m906-01 combines th e flexibility of a vcso (voltage controlled saw oscill ator) with the stability of a crystal oscillator. input reference the input reference can either be an external, discrete crystal device or a stable ex ternal clock source such as a packaged crystal oscillator: ? if an external crystal is used with the on-chip crystal oscillator circuit (xtal osc), the external crystal should be a parallel-resonant, fundamental mode crystal. apply it to the xtal_1 / ref_in and xtal_2 input pins. external crystal load capacitors are also required. ? if an external lvcmos/lvttl clock source is used, apply it to the xtal_1 / ref_in input pin. in either case, the reference clock is supplied to the phase detector of the pll. the m906-01 includes a reference divider that divides the input reference frequency by a fixed value ?r? and provides the result to the phase detector. the ex_clk pin is available for a clock feed-through mode for testing. see ?external clock feed-through? on pg. 4. the pll the pll (phase locked loop) includes the phase detector, the vcso, a feedback divider (labeled ?m divider?), and a reference divider (?r divider?). the feedback divider divides the vcso output frequency by a fixed value ?m? to match the reference frequency provided to the phase detector by the reference divider. by controlling the frequency and phase of the vcso, the phase detector precisely locks the frequency and phase of the feedback divider output to that of the reference divider output. this creates an output frequency that is a multiple of the reference frequency (which is output from the vcso). the relationship between the vcso output frequency, the m divider, the r divider and the input reference frequency is defined as follows: for the m906-01-156.2500 (see ?ordering information? on pg. 6): ? vcso output frequency = 156.25mhz ? input reference frequency = 25mhz ? m=25 ? r= 4 therefore, for the m906-01-156.2500 : 25 156.25mhz = 25mhz 4 the product of the input crystal frequency and falls within the lock range of the vcso. external loop filter to provide stable pll operation, and thereby a low jitter output clock, the m906-01 requires the use of an external loop filter. this is provided via the provided filter pins (see figure 4). due to the differential signal path design, the implementation requires two identical complementary rc filters as shown here. figure 4: external loop filter fvcso fxtal m r ---- - = external loop filter component values pll bandwidth damping factor r loop c loop r post c post 500 hz 2.1 1.5 k ? 4.00 f 50 k ? 3300 pf 1.5 khz 3.3 4.7 k ? 1.00 f 50 k ? 1500 pf 6.4 khz 4.4 20.0 k ? 0.10 f 20 k ? 470 pf 10.6 khz 1 note 1: recommended for most applications 4.2 33.0 k ? 0.033 f 20 k ? 470 pf table 3: external loop filter component values --------- - c post c post v c nvc r post nop_out op_out r post r loop r loop c loop c loop op_in nop_in 6 7 5 49 8
m906-01 datasheet rev 1.3 4 of 6 revised 06jan2004 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m906-01 vcso b ased g b e c lock g enerator preliminary information external clock feed-through the ext_clk pin provides an input for an external single-ended clock that di rectly drives the lvpecl clock outputs. in application, this may be used for system debugging and performance evaluation. 1. set pin en_ext_clk to logic 1. 2. apply an external lvcmos/lvttl clock source to the ext_clk input pin. due to the fact that ext_clk bypasses the pll, any frequency between dc and 200mhz can be used. stop clock the stop pin puts the output clock into a static condition. logic 1 output clocks are static logic 0 output clocks enabled for normal operation a bsolute m aximum r atings 1 symbol parameter rating unit v i inputs - 0.5 to v cc + 0.5 v v o outputs - 0.5 to v cc + 0.5 v v cc power supply voltage 4.6 v t s storage temperature - 45 to + 100 o c table 4: absolute maximum ratings note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress s pecifications only. func tional operation of produc t at these conditions or any conditions beyond those listed in recommended c onditions of operation, dc characteristics, or ac characteristics is not implied. exposure to abs olute maximum rating condi tions for extended periods may affect product reliability . r ecommended c onditions of o peration symbol parameter min typ max unit v cc positive supply voltage 3.135 3.3 3.465 v t a ambient operating temperature commercial 0 + 70 o c industrial -40 + 85 o c table 5: recommended conditions of operation
m906-01 datasheet rev 1.3 5 of 6 revised 06jan2004 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 m906-01 vcso b ased g b e c lock g enerator preliminary information integrated circuit systems, inc. e lectrical s pecifications dc characteristics unless stated otherwise, v cc = 3.3 v + 5 %,t a = 0 o c to + 70 o c (commercial) 1 , t a = -40 o c to + 85 o c (industrial) 1 , output frequency=156.25mhz 1 , lvpecl outputs terminated with 50 ? to v cc - 2v symbol parameter min typ max unit power supply v cc positive supply voltage 3.135 3.3 3.465 v i cc power supply current 350 ma logic inputs v ih input high voltage en_ext_clk, ext_clk, stop 2 v cc + 0.3 v v il input low voltage - 0.3 0.8 v i ih input high current 150 a i il input low current - 5.0 a reference clock input v ih input high voltage xtal_1 / ref_in (xtal_2 disconnected) (v cc / 2 ) + 0.5 v cc + 0.3 v v il input low voltage - 0.3 (v cc / 2 ) + 0.5 v i ih input high current 150 a i il input low current - 5.0 a all inputs c in input capacitance, all inputs en_ext_clk, ext_clk, stop, xtal_1 / ref_in 4 pf pull-down r pulldown internal pull-down resistor en_ext_clk, stop 51 k ? differential output v oh output high voltage fout, nfout (0-5) v cc - 1.4 v cc - 1.0 v v ol output low voltage v cc - 2.0 v cc - 1.7 v v p - p peak to peak output voltage 0.6 0.85 v table 6: dc characteristics note 1: see ordering information on pg. 6 ac characteristics unless stated otherwise, v cc = 3.3 v + 5 %,t a = 0 o c to + 70 o c (commercial) 1 , t a = -40 o c to + 85 o c (industrial) 1 , output frequency=156.25mhz 1 , lvpecl outputs terminated with 50 ? to v cc - 2v symbol parameter min typ max unit test conditions f out output frequency range 125 156.25 190 mhz f in nominal input frequency, xtal_1 / ref_in 25 mhz apr vcso pull-range 100 150 ppm n single side band phase noise @ 156.25 mhz 1 khz offset - 100 dbc/hz 10 khz offset - 110 dbc/hz 100 khz offset - 134 dbc/hz j(t) jitter (rms) 0.7 1.0 ps 12 khz to 20 mhz t dc output duty cycle, high time 45 50 55 % t r output rise time fout, nfout (0-1) 350 450 550 ps 20 % to 80 % t f output fall time fout, nfout (0-1) 350 450 550 ps 20 % to 80 % t s output skew between any pair 100 ps ext_clk frequency ext_clk 0 200 mhz table 7: ac characteristics note 1: see ordering information on pg. 6
m906-01 datasheet rev 1.3 6 of 6 revised 06jan2004 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 integrated circuit systems, inc. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high reliability, or other extraordina ry environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. m906-01 vcso b ased g b e c lock g enerator preliminary information d evice p ackage - 9 x 9mm c eramic l eadless c hip c arrier mechanical dimensions: figure 5: device package - 9 x 9mm ceramic leadless chip carrier o rdering i nformation part numbering scheme figure 6: part numbering scheme consult factory for frequency availability. part number: m906- 01 - xxx.xxxx output frequency (mhz) ? - ? = 0 to + 70 o c (commercial) see table 8, right. consult ics for other frequencies. i = - 40 to + 85 o c (industrial) temperature device number example part numbers output freq. (mhz) temperature order part number 156.25 commercial m906-01 - 156.2500 industrial m906-01 i 156.2500 156.25 commercial m906-01 - 156.2500 industrial m906-01 i 156.2500 187.50 commercial m906-01 - 187.5000 industrial m906-01 i 187.5000 table 8: example part numbers
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